2013 Recipients

Best Paper and Poster Awards

As a full conference or one-day only registrant, you are entitled to vote for the DVCon Best Paper and Poster awards. The Attendees are the judges!
 

2013 Recipients:

Sponsored by:
 

Winning Paper Presentation:

11.2

SVA Encapsulation in UVM - Enabling Phase and Configuration Aware

Speaker:

Mark Litterick - Verilab, Inc.

Authors:

Mark Litterick - Verilab, Inc.

Winning Poster Presentations:

 

Unconstrained UVM SystemVerilog Performance

Speaker:

Wes Queen - IBM Corp.

Authors:

Wes Queen - IBM Corp.
Justin A. Sprague - Cadence Design Systems, Inc.
John Pierce - Cadence Design Systems, Inc.

 

Monitors, Monitors Everywhere – Who is Monitoring the Monitors? SystemVerilog UVM Monitors and Scoreboards

Speaker:

Rich Edelman - Mentor Graphics Corp.

Authors:

Rich Edelman - Mentor Graphics Corp.
Raghu Ardeishar - Mentor Graphics Corp.

Honorable Mentions:

4.3

Who’s Watching the Watchmen? The Time has Come to Objectively Measure the Quality of Your Verification Environment

Speaker:

David C. Brownell - Analog Devices, Inc.

Authors:

David C. Brownell - Analog Devices, Inc.

8.1

The Finer Points of UVM: Tasting Tips for the Connoisseur

Speaker:

John Aynsley - Doulos

Authors:

John Aynsley - Doulos

 

Sponsored by:


1st Place:

12.1

SystemVerilog Assertion Linting: Closing Potentially Critical Verification Holes

Speaker:

Erik Seligman - Intel Corp.

Authors:

Laurence Bisht - Intel Corp.
Dmitry Korchemny - Intel Corp.
Erik Seligman - Intel Corp.

2nd Place:

12.3

Better Living Through Better Class-Based SystemVerilog Debug

Speaker:

Rich Edelman - Mentor Graphics Corp.

Authors:

Rich Edelman - Mentor Graphics Corp.
Raghu Ardeishar - Mentor Graphics Corp.
John Amouroux - Mentor Graphics Corp.

Honorable Mentions:

4.1

Yikes! Why is My SystemVerilog Testbench so Slow?

Speaker:

Justin Sprague - Cadence Design Systems, Inc.

Authors:

Frank Kampf - IBM Corp.
Justin Sprague - Cadence Design Systems, Inc.
Adam Sherer - Cadence Design Systems, Inc.

4.3 

Keeping Up with Chip - The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient

Speaker:

Stuart Sutherland - Sutherland Hdl, Inc.

Authors:

Stuart Sutherland - Sutherland Hdl, Inc.
Tom Fitzpatrick - Mentor Graphics Corp.

 

Effects of Abstraction in Stimulus Generation of Layered Protocols within OVM
Josh Rensch - Lockheed Martin Corp.
Jesse Prusi - Lockheed Martin Corp.

Low Power Verification Methodology using UPF
Freddy Bembaron - Texas Instruments, Inc.
Rudra Mukherjee, Amit Srivastava, Sachin Kakkar - Mentor Graphics Corp.

Paper 2.2 - Bridging the Application and Design Gap: Utilization of the GBD Proxy Protocol for Remote Control of an RTL Simulation
Kelly Larson - MediaTek, Inc.

Paper 1.3 - Towards a Practical Design Methodology with SystemVerilog Interfaces and Modports
Jonathan Bromley - Doulos Ltd. Paper 6.2 - FEV's Greatest Bloopers: False Positives in Formal Equivalence
Erik Seligman, Joonyoung Kim - Intel Corp.

Session 9 - Innovative Verification Solutions
Paper 9.1 - Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter using SystemVerilog Assertions
Mark Litterick - Verilab GmbH

Verification Area
Session 3 - Innovative Verification Solutions
Paper 3.3 - Using MatLab and Simulink in a SystemC Verification Environment
Jean Francois Boland - McGill Univ., Montreal, Quebec, Canada
Claude Thibeault - Ecole de Technologie Superieure. Montreal, Quebec, Canada
Zeljko Zilic - McGill Univ., Montreal, Quebec, Canada

Design Area
Session 10 - SystemVerilog in Action
Paper 10.2 - Using SystemVerilog Now with DPI
Rich Edelman, Doug Warmke - Mentor Graphics Corp., San Jose, CA

VerificationArea
Session 2 - Coverage and Assertion-Based Verification
Paper 2.3 - Coverage-Based DV from Testplan to Tapeout using Random Generation and RTL Assertions
Carey Kloss, Dean Chao - Cisco Systems, San Jose, CA

Design Area
Session 1 - Real World Design
Paper 1.1 - Design and Verification of a DSP using VHDL, Verilog, SystemC, and C++
Greg Tumbush, Bill Dittenhofer - Starkey Labs, Colorado Springs, COtechnical program with sponsored tutorials, technical panels, embedded tutorials, and research sessions, as well as informative (and delicious) sponsored luncheons.