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1st Place:

12.1

SystemVerilog Assertion Linting: Closing Potentially Critical Verification Holes

Speaker:

Erik Seligman - Intel Corp.

Authors:

Laurence Bisht - Intel Corp.
Dmitry Korchemny - Intel Corp.
Erik Seligman - Intel Corp.

2nd Place:

12.3

Better Living Through Better Class-Based SystemVerilog Debug

Speaker:

Rich Edelman - Mentor Graphics Corp.

Authors:

Rich Edelman - Mentor Graphics Corp.
Raghu Ardeishar - Mentor Graphics Corp.
John Amouroux - Mentor Graphics Corp.

Honorable Mentions:

4.1

Yikes! Why is My SystemVerilog Testbench so Slow?

Speaker:

Justin Sprague - Cadence Design Systems, Inc.

Authors:

Frank Kampf - IBM Corp.
Justin Sprague - Cadence Design Systems, Inc.
Adam Sherer - Cadence Design Systems, Inc.

4.3 

Keeping Up with Chip - The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient

Speaker:

Stuart Sutherland - Sutherland Hdl, Inc.

Authors:

Stuart Sutherland - Sutherland Hdl, Inc.
Tom Fitzpatrick - Mentor Graphics Corp.